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Pin Connections and Guidelines
SV51010
2014.01.10
Pin Connections and Guidelines
Observe the following pin connections and guidelines for this configuration setup:
? Isolate the CONF_DONE and nSTATUS pins to allow each device to enter user mode independently.
? One JTAG-compatible header is connected to several devices in a JTAG chain. The number of devices
in the chain is limited only by the drive capability of the download cable.
? If you have four or more devices in a JTAG chain, buffer the TCK , TDI , and TMS pins with an on-board
buffer. You can also connect other Altera devices with JTAG support to the chain.
? JTAG-chain device programming is ideal when the system contains multiple devices or when testing
your system using the JTAG boundary-scan testing (BST) circuitry.
Using a Download Cable
The following figure shows a multi-device JTAG configuration.
Figure 8-19: JTAG Configuration of Multiple Devices Using a Download Cable
If you only use the JTAG configuration, connect nCONFIG to VCCPGM and MSEL[4..0]
to GND. Pull DCLK either high or low, whichever is convenient on your board. If you are
Connect the pull-up
resistor V CCPD .
using JTAG in conjunction with another configuration scheme, connect MSEL[4..0],
nCONFIG, and DCLK based on the selected configuration scheme.
Download Cable
10-Pin Male Header
V CCPGM
FPGA Device
V CCPGM V CCPGM
FPGA Device
V CCPGM V CCPGM
FPGA Device
V CCPGM
(JTAG Mode)
Pin 1
V CCPD
V CCPD
10 kΩ 10 kΩ
nSTATUS
nCONFIG
DCLK CONF_DONE
MSEL[4..0]
10 kΩ 10 kΩ
nSTATUS
nCONFIG
DCLK CONF_DONE
MSEL[4..0]
10 kΩ 10 kΩ
nSTATUS
nCONFIG
DCLK CONF_DONE
MSEL[4..0]
V CCPD
nCE
V CCPD
nCE
V CCPD
nCE
TRST
TRST
TRST
V IO
V CCPD
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
1 kΩ
Connect the pull-up
resistor V CCPD .
You must connect nCE to
The resistor value can vary from 1 kΩ to 10
kΩ. Perform signal integrity analysis to
GND or drive it low for
successful JTAG configuration.
select the resistor value for your setup.
Related Information
AN 656: Combining Multiple Configuration Schemes
Provides more information about combining JTAG configuration with other configuration schemes.
CONFIG_IO JTAG Instruction
The CONFIO_IO JTAG instruction allows you to configure the I/O buffers using the JTAG port before or
during device configuration. When you issue this instruction, it interrupts configuration and allows you to
issue all JTAG instructions. Otherwise, you can only issue the BYPASS , IDCODE , and SAMPLE JTAG instructions.
Altera Corporation
Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
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